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SH7672 Datasheet(PDF) 256 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 256 Page - Renesas Technology Corp |
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256 / 1292 page ![]() Section 7 Bus State Controller (BSC) Rev. 1.00 Nov. 14, 2007 Page 230 of 1262 REJ09B0437-0100 When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 7.10. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle. T1 CKIO A25 to A0 CSn RD/ WR RD D31 to D0 WEn D31 to D0 WAIT Tw Tw Twx T2 Read Write BS Wait states inserted by WAIT signal DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.10 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT Signal) |
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