SH7672 datasheet(261/1292 Pages) RENESAS

261 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 235 of 1262

REJ09B0437-0100

(2)

Address Multiplexing

An address multiplexing is specified so that SDRAM can be connected without external

multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, bits A2ROW[1:0],

and A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 7.11 to 7.16 show the

relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and

A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other

than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not

multiplexed and the original values of address are always output at these pins.

When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word

address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of

SDRAM to the A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ1 and BSZ0

= B'11), the A0 pin of SDRAM specifies a longword address. Therefore, connect this A0 pin of

SDRAM to the A2 pin of the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.

SH7672 Datasheet(PDF) 261 Page - Renesas Technology Corp