SH7672 datasheet(278/1292 Pages) RENESAS

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Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 252 of 1262

REJ09B0437-0100

(5)

Burst Write

A burst write occurs in the following cases in this LSI.

• Access size in writing is larger than data bus width.

• Write-back of the cache

• 16-byte transfer in DMAC

This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1

is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is

connected to a 32-bit data bus. This access is called burst write with the burst number 4. The

relationship between the access size and the number of bursts is shown in table 7.17. Figure 7.17

shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle,

the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued

to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output

simultaneously with the write command. After the write command with the auto-precharge is

output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that

waits for completion of the auto-precharge induced by the WRITA command in the SDRAM.

Between the Trwl and the Tap cycle, a new command will not be issued to the same bank.

However, access to another CS space or another bank in the same SDRAM space is enabled. The

number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of

Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR.

SH7672 Datasheet(PDF) 278 Page - Renesas Technology Corp