SH7672 datasheet(314/1292 Pages) RENESAS

314 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 288 of 1262

REJ09B0437-0100

Table 7.21

Minimum Number of Idle Cycles on Internal Bus (CPU Operation)

Clock Ratio (I

φ:Bφ)

CPU Operation

8:1

6:1

4:1

3:1

2:1

1:1

Write

→ write

Write

→ read

Read

→ write

Read

→ read

Table 7.22

Minimum Number of Idle Cycles on Internal Bus (DMAC Operation)

Transfer Mode

DMAC Operation

Dual Address

Single Address

Write

→ write

Write

→ read

0 or 2

Read

→ write

Read

→ read

Notes: 1. The write

→ write and read → read columns in dual address transfer indicate the cycles

in the divided access cycles.

2. For the write

→ read cycles in dual address transfer, 0 means different channels are

activated successively and 2 means when the same channel is activated successively.

3. The write

→ read and read → write columns in single address transfer indicate the case

when different channels are activated successively. The "write" means transfer from a

device with DACK to external memory and the "read" means transfer from external

memory to a device with DACK.

Table 7.23

Number of Idle Cycles Inserted between Access Cycles to Different Memory

Types

Next Cycle

Previous Cycle

SRAM

Byte SRAM (BAS = 0)

Byte SRAM (BAS = 1)

SDRAM

PCMCIA

SRAM

Byte SRAM (BAS = 0)

Byte SRAM (BAS = 1)

SDRAM

PCMCIA

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