SH7672 datasheet(318/1292 Pages) RENESAS

318 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 292 of 1262

REJ09B0437-0100

(3)

On-Chip Peripheral Module Access

To access an on-chip module register, two or more peripheral module clock (P

φ) cycles are

required. Care must be taken in system design.

When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding

instructions without waiting for the completion of writing to registers.

For example, a case is described here in which the system is transferring to the software standby

mode for power savings. To make this transition, the SLEEP instruction must be performed after

setting the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is

required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes

the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not

software standby mode. A dummy read of the STBCR register is indispensable to complete

writing to the STBY bit.

To reflect the change by internal peripheral registers while performing the succeeding instructions,

execute a dummy read of registers to which write instruction is given and then perform the

succeeding instructions.

SH7672 Datasheet(PDF) 318 Page - Renesas Technology Corp