SH7672 datasheet(321/1292 Pages) RENESAS

321 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 295 of 1262

REJ09B0437-0100

Figure 8.1 shows the block diagram of the DMAC.

On-chip

peripheral module

DMA transfer request signal

DMA transfer acknowledge signal

External ROM

On-chip

memory

Interrupt controller

DREQ0 to DREQ3

HEIn

DACK0 to DACK3,

TEND0, TEND1

External RAM

Bus

interface

Bus state

controller

External device

(memory mapped)

External device

(with acknowledge)

Request

priority

control

Start-up

control

Iteration

control

RDMATCR_n

DMATCR_n

RSAR_n

SAR_n

DAR_n

RDAR_n

CHCR_n

DMAOR

DMARS0

to DMARS3

RDMATCR:

DMATCR:

RSAR:

SAR:

RDAR:

DAR:

DMA reload transfer count register

DMA transfer count register

DMA reload source address register

DMA source address register

DMA reload destination address register

DMA destination address register

CHCR:

DMAOR:

DMARS0 to DMARS3:

HEIn:

DEIn:

n = 0 to 7

DMA channel control register

DMA operation register

DMA extension resource selectors 0 to 3

DMA transfer half-end interrupt request to the CPU

DMA transfer end interrupt request to the CPU

DEIn

[Legend]

DMAC module

Figure 8.1 Block Diagram of DMAC

SH7672 Datasheet(PDF) 321 Page - Renesas Technology Corp

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