SH7672 datasheet(319/1292 Pages) RENESAS

319 / 1292 page

Section 8 Direct Memory Access Controller (DMAC)

Rev. 1.00 Nov. 14, 2007 Page 293 of 1262

REJ09B0437-0100

Section 8 Direct Memory Access Controller (DMAC)

The DMAC can be used in place of the CPU to perform high-speed transfers between external

devices that have DACK (transfer request acknowledge signal), external memory, on-chip

memory, memory-mapped external devices, and on-chip peripheral modules.

8.1

Features

• Number of channels: Eight channels (channels 0 to 7) selectable

Two channels (channels 0 and 1) can receive external requests.

• 4-Gbyte physical address space

• Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes

(longword

× 4)

• Maximum transfer count: 16,777,216 transfers (24 bits)

• Address mode: Dual address mode and single address mode are supported.

• Transfer requests

 External request

 On-chip peripheral module request

 Auto request

The following modules can issue on-chip peripheral module requests.

 Six SCIF sources, two IIC3 sources, two CMT sources, two SSI sources, and two SDHI

sources

• Selectable bus modes

 Cycle steal mode (normal mode and intermittent mode)

 Burst mode

• Selectable channel priority levels: The channel priority levels are selectable between fixed

mode and round-robin mode.

• Interrupt request: An interrupt request can be sent to the CPU on completion of half- or full-

data transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to

the CPU when half of the initially specified DMA transfer is completed.

• External request detection: There are following four types of DREQ input detection.

 Low level detection

 High level detection

 Rising edge detection

 Falling edge detection

SH7672 Datasheet(PDF) 319 Page - Renesas Technology Corp