38K2 datasheet(342/358 Pages) RENESAS

342 / 358 page

3.4 List of registers

Rev.2.00

Oct 15, 2006

page 81 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

Fig. 3.4.102 Structure of PLL control register

b7 b6 b5 b4 b3 b2 b1 b0

USB clock division

ratio selection bits

PLL control register (PLLCON)

[Address : 0FF816]

Function

At reset

Name

PLL control register

b4 b3

0 0 : Divided by 8 (fSYN = fUSB/8)

0 1 : Divided by 6 (fSYN = fUSB/6)

1 0 : Divided by 4 (fSYN = fUSB/4)

1 1 : Not selected

Nothing is arranged for these bit. These are write disabled bits.

When these bits are read out, the contents are “0”.

b6 b5

0 0 : Not multiplied (fVCO = fXIN)

0 1 : Double (fVCO = fXIN ✕ 2)

1 0 : Quadruple (fVCO = fXIN ✕ 4)

1 1 : Multiplied by 8 (fVCO = fXIN ✕ 8)

PLL operation mode

selection bits

PLL enable bit

0 : Disabled

1 : Enabled

PCON1

[1:0]

PCON2

[1:0]

b7:b4

–

Downstream port control register (DPCTL) [address 0FF916]

Bit name

Bit symbol

At reset

Function

H/W

S/W

Downstream port 1 function

select bit

Downstream port 2 function

select bit

Not used

b1b0

0 0 : USB port (D1-, D1+) OFF,

USB difference amplifier OFF

0 1 : USB exclusive input port (D1-, D1+),

USB difference amplifier OFF

1 0 : Full-speed port (D1-, D1+),

USB difference amplifier ON

1 1 : Low-speed port (D1-, D1+),

USB difference amplifier ON

b3b2

0 0 : USB port (D2-, D2+) OFF,

USB difference amplifier OFF

0 1 : USB exclusive input port (D2-, D2+),

USB difference amplifier OFF

1 0 : Full-speed port (D2-, D2+),

USB difference amplifier ON

1 1 : Low-speed port (D2-, D2+),

USB difference amplifier ON

Write “0” when writing.

“0” is read when reading.

–: State remaining

Fig. 3.4.103 Structure of Downstream port control register

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