38K2 datasheet(343/358 Pages) RENESAS

343 / 358 page

3.4 List of registers

Rev.2.00

Oct 15, 2006

page 82 of 99

38K2 Group

REJ09B0338-0200

APPENDIX

Fig. 3.4.104 Structure of MISRG

b7 b6 b5 b4 b3 b2 b1 b0

R W

Name

Functions

At reset

MISRG

(MISRG: address 0FFB16)

MISRG

0 : Automatically set “0116” to Timer 1,

“FF16” to Prescaler 12

1 : Automatically set nothing

Nothing is arranged for these bits. These are write disabled bits.

When these bits are read out, the contents are indefinite.

Oscillation stabilizing time

set after STP instruction

released bit

Fig. 3.4.105 Structure of Flash memory control register

Flash memory control register

b7 b6 b5 b4 b3 b2 b1 b0

Flash memory control register

(FMCR : address 0FFE16)

(Note 1)

Name

Functions

At reset R W

User area/Boot area

selection bit (Note 4)

CPU rewrite mode

select bit (Note 2)

0 : Busy (being written or

erased)

1 : Ready

Undefined

RY/BY status flag

0: User ROM area

1: Boot ROM area

Flash memory reset

bit (Note 3)

0: Normal operation

1: Reset

CPU rewrite mode

entry flag

0: Normal mode

1: CPU rewrite mode

0 : Normal mode (Software

commands invalid)

1 : CPU rewrite mode

(Software commands

acceptable)

Nothing is arranged for these bits. If writing,

set “0”. When these bits are read out,

the contents are undefined.

Notes 1: The contents of flash memory control register are “XXX00001” just

after reset release.

2: For this bit to be set to “1”, the user needs to write “0” and then “1”

to it in succession. If it is not this procedure, this bit will not be set to

“1”. Additionally, it is required to ensure that no interrupt will be

generated during that interval.

Use the control program in the area except the built-in flash memory

for write to this bit.

3: This bit is valid when the CPU rewrite mode select bit is “1”.

Set this bit 3 to “0” subsequently after setting bit 3 to “1”.

4: Use the control program in the area except the built-in flash memory

for write to this bit.

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