38K2 datasheet(216/358 Pages) RENESAS

216 / 358 page

2.4 Serial I/O

Rev.2.00

Oct 15, 2006

page 67 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

(2)

Notes when selecting clock asynchronous serial I/O (Serial I/O)

➀ Stop of transmission operation

Clear the transmit enable bit to “0” (transmit disabled).

q Reason

Since transmission is not stopped and the transmission circuit is not initialized even if only the

serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in

this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not

output). When data is written to the transmit buffer register in this state, data starts to be shifted

to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during

internally shifting is output to the TxD pin and an operation failure occurs.

➁ Stop of receive operation

Clear the receive enable bit to “0” (receive disabled).

➂ Stop of transmit/receive operation

Only transmission operation is stopped.

Clear the transmit enable bit to “0” (transmit disabled).

q Reason

Since transmission is not stopped and the transmission circuit is not initialized even if only the

serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in

this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not

output). When data is written to the transmit buffer register in this state, data starts to be shifted

to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during

internally shifting is output to the TxD pin and an operation failure occurs.

Only receive operation is stopped.

Clear the receive enable bit to “0” (receive disabled).

(3)

SRDY output of reception side (Serial I/O)

When signals are output from the SRDY pin on the reception side by using an external clock in the

clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and

the transmit enable bit to “1” (transmit enabled).

(4)

Setting serial I/O control register again (Serial I/O)

Set the serial I/O control register again after the transmission and the reception circuits are reset by

clearing both the transmit enable bit and the receive enable bit to “0.”

Fig. 2.4.35 Sequence of setting serial I/O control register again

Clear both the transmit enable bit (TE)

and the receive enable bit (RE) to “0”

↓

Set the bits 0 to 3 and bit 6 of the

serial I/O control register

↓

Set both the transmit enable bit (TE) and

the receive enable bit (RE), or one of

them to “1”

Can be set with the LDM instruction at the same time

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