38K2 datasheet(217/358 Pages) RENESAS

217 / 358 page

2.4 Serial I/O

Rev.2.00

Oct 15, 2006

page 68 of 112

38K2 Group

REJ09B0338-0200

APPLICATION

(5)

Data transmission control with referring to transmit shift register completion flag (Serial I/O)

The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift

clocks. When data transmission is controlled with referring to the flag after writing the data to the

transmit buffer register, note the delay.

(6)

Transmission control when external clock is selected (Serial I/O)

When an external clock is used as the synchronous clock for data transmission, set the transmit

enable bit to “1” at “H” of the SCLK input level. Also, write the transmit data to the transmit buffer

(7)

Transmit interrupt request when transmit enable bit is set (Serial I/O)

When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown

in the following sequence.

➀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.

➁ Prepare serial I/O for transmission/reception.

➂ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been

executed.

➃ Set the interrupt enable bit to “1” (enabled).

q Reason

When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift

interrupt bit is set regardless of which of the two timings listed below is selected as the timing for

the transmission interrupt to be generated.

• Transmit buffer empty flag is set to “1”

• Transmit shift register completion flag is set to “1”

38K2 Datasheet(PDF) 217 Page - Renesas Technology Corp