H83065 datasheet(52/963 Pages) RENESAS

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Section 2 CPU

Rev. 4.00 Jan 26, 2006 page 30 of 938

REJ09B0276-0400

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and

XORC instructions.

Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign

bit.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and

cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,

STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional

branch (Bcc) instructions.

For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and

UI bits, see section 5, Interrupt Controller.

2.4.4

Initial CPU Register Values

In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit

in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,

the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must

therefore be initialized by an MOV.L instruction executed immediately after a reset.

H83065 Datasheet(PDF) 52 Page - Renesas Technology Corp