H83065 datasheet(23/963 Pages) RENESAS

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Section 1 Overview

Rev. 4.00 Jan 26, 2006 page 1 of 938

REJ09B0276-0400

Section 1 Overview

1.1

Overview

The H8/3067 Group is a group of microcontrollers (MCUs) that integrate system supporting

functions together with an H8/300H CPU core having an original Renesas architecture.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,

enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a

programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication

interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller

(DMAC), and other facilities.

The three members of the H8/3067 Group are the H8/3067, the H8/3066, and the H8/3065. The

H8/3067 has 128 kbytes of ROM and 4 kbytes of RAM. The H8/3066 has 96 kbytes of ROM and

4 kbytes of RAM. The H8/3065 has 64 kbytes of ROM and 2 kbytes of RAM.

Seven MCU operating modes offer a choice of bus width and address space size. The modes

(modes 1 to 7) include two single-chip modes and five expanded modes.

In addition to the mask ROM versions, the H8/3067 Group includes an F-ZTAT™* version with

on-chip flash memory that can be programmed on-board. This version enables users to respond

quickly and flexibly to changing application specifications, growing production volumes, and

other conditions.

Table 1.1 summarizes the features of the H8/3067 Group.

Note: * F-ZTAT™ (Flexible ZTAT) is a trademark of Renesas Technology Corp.

H83065 Datasheet(PDF) 23 Page - Renesas Technology Corp