H83065 datasheet(80/963 Pages) RENESAS

80 / 963 page

Section 2 CPU

Rev. 4.00 Jan 26, 2006 page 58 of 938

REJ09B0276-0400

−4

−3

−2

−1

SP (ER7)

Before exception

handling starts

SP (ER7)

SP+1

SP+2

SP+3

SP+4

After exception

handling ends

Stack area

CCR

Even

address

Pushed on stack

Legend

CCR:

SP:

Condition code register

Stack pointer

Notes: 1.

PC is the address of the first instruction executed after the return from the

exception-handling routine.

Registers must be saved and restored by word access or longword access,

starting at an even address.

Figure 2.14 Stack Structure after Exception Handling

2.8.5

Bus-Released State

In this state the bus is released to a bus master other than the CPU, in response to a bus request.

The bus masters other than the CPU are the DMA controller, the DRAM interface, and an external

bus master. While the bus is released, the CPU halts except for internal operations. Interrupt

requests are not accepted. For details see section 6.11, Bus Arbiter.

2.8.6

Reset State

When the

RES input goes low all current processing stops and the CPU enters the reset state. The I

bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.

Reset exception handling starts when the

RES signal changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details see section 12,

Watchdog Timer.

H83065 Datasheet(PDF) 80 Page - Renesas Technology Corp

H83065 Datasheet(HTML) 80 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL