H83065 datasheet(82/963 Pages) RENESAS

Part #	H83065

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	963 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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82 / 963 page

Section 2 CPU

Rev. 4.00 Jan 26, 2006 page 60 of 938

REJ09B0276-0400

2.9

Basic Operational Timing

2.9.1

Overview

The H8/300H CPU operates according to the system clock (

φ). The interval from one rise of the

system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of

two or three states. The CPU uses different methods to access on-chip memory, the on-chip

supporting modules, and the external address space. Access to the external address space can be

controlled by the bus controller.

2.9.2

On-Chip Memory Access Timing

On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and

word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin

states.

T state

Bus cycle

Internal address bus

Internal read signal

Internal data bus

(read access)

Internal write signal

Internal data bus

(write access)

T state

Read data

Address

Write data

Figure 2.15 On-Chip Memory Access Cycle

H83065 Datasheet(PDF) 82 Page - Renesas Technology Corp