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H83065 Datasheet(PDF) 78 Page - Renesas Technology Corp |
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H83065 Datasheet(HTML) 78 Page - Renesas Technology Corp |
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78 / 963 page ![]() Section 2 CPU Rev. 4.00 Jan 26, 2006 page 56 of 938 REJ09B0276-0400 Exception sources Reset Interrupt Trap instruction External interrupts Internal interrupts (from on-chip supporting modules) Figure 2.12 Classification of Exception Sources Bus-released state Exception-handling state Reset state*1 Program execution state Sleep mode Software standby mode Hardware standby mode*2 Power-down state Bus request End of bus release End of bus release Bus request End of exception handling Exception handling source Interrupt source SLEEP instruction with SSBY = 0 SLEEP instruction with SSBY = 1 NMI, IRQ , IRQ , or IRQ interrupt STBY="High", RES ="Low" RES = "High" 01 2 Notes: 1. 2. From any state except hardware standby mode, a transition to the reset state occurs whenever goes low. From any state, a transition to hardware standby mode occurs when goes low. RES STBY Figure 2.13 State Transitions |
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