SH7014 datasheet(335/754 Pages) RENESAS

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SH7014 Datasheet(PDF) 335 Page - Renesas Technology Corp

Part #	SH7014

Description	32-Bit RISC Microcomputer

PDF	754 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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335 / 754 page

11. Watchdog Timer (WDT)

Rev.5.00 Sep. 27, 2007 Page 301 of 716

REJ09B0398-0500

11.3.4

Timing of Setting the Overflow Flag (OVF)

In the interval timer mode, when the TCNT overflows, the OVF flag of the TCSR is set to 1 and

an interval timer interrupt is simultaneously requested (figure 11.6).

H'FF

H'00

TCNT

Overflow signal

(internal signal)

OVF

Figure 11.6 Timing of Setting the OVF

11.3.5

Timing of Setting the Watchdog Timer Overflow Flag (WOVF)

When the TCNT overflows in the watchdog timer mode, the WOVF bit of the RSTCSR is set to 1

and a

WDTOVF signal is output. When the RSTE bit is set to 1, TCNT overflow enables an

internal reset signal to be generated for the entire chip (figure 11.7).

H'FF

H'00

TCNT

Overflow signal

(internal signal)

WOVF

Figure 11.7 Timing of Setting the WOVF Bit

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