SH7014 datasheet(331/754 Pages) RENESAS

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11. Watchdog Timer (WDT)

Rev.5.00 Sep. 27, 2007 Page 297 of 716

REJ09B0398-0500

11.2.4

The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in that they

are more difficult to write to. The procedures for writing and reading these registers are given

below.

Writing to the TCNT and TCSR: These registers must be written by a word transfer instruction.

They cannot be written by byte transfer instructions.

The TCNT and TCSR both have the same write address. The write data must be contained in the

lower byte of the written word. The upper byte must be H'5A (for the TCNT) or H'A5 (for the

TCSR) (figure 11.2). This transfers the write data from the lower byte to the TCNT or TCSR.

H'5A

H'FFFF8610

Address:

Writing to the TCNT

Write data

H'A5

H'FFFF8610

Address:

Writing to the TCSR

Write data

Figure 11.2 Writing to the TCNT and TCSR

Writing to the RSTCSR: The RSTCSR must be written by a word access to address

H'FFFF8612. It cannot be written by byte transfer instructions.

Procedures for writing 0 in WOVF (bit 7) and for writing to RSTE (bit 6) are different, as shown

in figure 11.3.

To write 0 in the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower

byte. This clears the WOVF bit to 0. The RSTE bit is not affected. To write to the RSTE bit, the

upper byte must be H'5A and the lower byte must be the write data. The values of bit 6 of the

lower byte is transferred to the RSTE bit, respectively. The WOVF bit is not affected.

SH7014 Datasheet(PDF) 331 Page - Renesas Technology Corp