SH7014 datasheet(328/754 Pages) RENESAS

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11. Watchdog Timer (WDT)

Rev.5.00 Sep. 27, 2007 Page 294 of 716

REJ09B0398-0500

11.2.2

Timer Control/Status Register (TCSR)

Bit:

OVF

WT/

TME

⎯

CKS2

CKS1

CKS0

Initial value:

R/W:

R/(W)

R/W

The timer control/status register (TCSR) is an 8-bit read/write register. (The TCSR differs from

other registers in that it is more difficult to write to. See section 11.2.4, Register Access, for

details.) Its functions include selecting the timer mode and clock source.

Bits 7 to 5 are initialized to 000 by a power-on reset or in standby mode. Bits 2 to 0 are initialized

to 000 by a power-on reset, but retain their values in the standby mode.

Bit 7

⎯Overflow Flag (OVF): Indicates that the TCNT has overflowed from H'FF to H'00 in the

interval timer mode. It is not set in the watchdog timer mode.

Bit 7

OVF

Description

No overflow of TCNT in interval timer mode

(initial value)

Cleared by reading OVF, then writing 0 in OVF

TCNT overflow in the interval timer mode

Bit 6

⎯Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or

interval timer. When the TCNT overflows, the WDT either generates an interval timer interrupt

(ITI) or generates a

WDTOVF signal, depending on the mode selected.

Bit 6

WT/

Description

Interval timer mode: interval timer interrupt request to the CPU when

TCNT overflows

(initial value)

Watchdog timer mode:

WDTOVF signal output externally when TCNT

overflows. (Section 11.2.3, Reset Control/Status Register (RSTCSR),

describes in detail what happens when TCNT overflows in the watchdog

timer mode.)

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