SH7014 datasheet(329/754 Pages) RENESAS

329 / 754 page

11. Watchdog Timer (WDT)

Rev.5.00 Sep. 27, 2007 Page 295 of 716

REJ09B0398-0500

Bit 5

⎯Timer Enable (TME): Enables or disables the timer.

Bit 5

TME

Description

Timer disabled: TCNT is initialized to H'00 and count-up stops

(initial value)

Timer enabled: TCNT starts counting. A

WDTOVF signal or interrupt is

generated when TCNT overflows.

Bits 4 and 3

⎯Reserved: These bits always read as 1. The write value should always be 1.

Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock

sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the

system clock (

φ).

Description

Bit 2

CKS2

Bit 1

CKS1

Bit 0

CKS0

Clock Source

Overflow Interval*

(

φ = 28.7 MHz)

φ/2

(initial value) 17.9

μs

φ/64

573.4

μs

φ/128

1.1 ms

φ/256

2.3 ms

φ/512

4.6 ms

φ/1024

9.2 ms

φ/4096

36.7 ms

φ/8192

73.4 ms

Note:

The overflow interval listed is the time from when the TCNT begins counting at H'00

until an overflow occurs.

SH7014 Datasheet(PDF) 329 Page - Renesas Technology Corp

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