SH7014 datasheet(327/754 Pages) RENESAS

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11. Watchdog Timer (WDT)

Rev.5.00 Sep. 27, 2007 Page 293 of 716

REJ09B0398-0500

11.1.4

Table 11.2 summarizes the three WDT registers. They are used to select the clock, switch the

WDT mode, and control the reset signal.

Table 11.2

WDT Registers

Address

Name

Abbreviation

R/W

Initial Value

Write*

Read*

Timer control/status

TCSR

R/(W)*

H'18

H'FFFF8610

Timer counter

TCNT

R/W

H'00

H'FFFF8611

Reset control/status

RSTCSR

R/(W)*

H'1F

H'FFFF8612

H'FFFF8613

Notes: 1. Write by word transfer. It cannot be written in byte or longword.

2. Read by byte transfer. It cannot be read in word or longword.

3. Only 0 can be written in bit 7 to clear the flag.

11.2

11.2.1

Timer Counter (TCNT)

Bit:

Initial value:

R/W:

R/W

The TCNT is an 8-bit read/write upcounter. (The TCNT differs from other registers in that it is

more difficult to write to. See section 11.2.4, Register Access, for details.) When the timer enable

bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts

counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in the

TCSR. When the value of the TCNT overflows (changes from H'FF to H'00), a watchdog timer

overflow signal (

WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode

selected in the WT/

IT bit of the TCSR.

The TCNT is initialized to H'00 by a power-on reset and when the TME bit is cleared to 0. It is not

initialized in the standby mode.

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