 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SH7014 Datasheet(PDF) 336 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
SH7014 Datasheet(HTML) 336 Page - Renesas Technology Corp |
|
|
336 / 754 page  11. Watchdog Timer (WDT) Rev.5.00 Sep. 27, 2007 Page 302 of 716 REJ09B0398-0500 11.4 Usage Notes 11.4.1 TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T 3 state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 11.8). CK Address Internal write signal TCNT input clock TCNT NM TCNT address Counter write data T1 T2 T3 TCNT write cycle Figure 11.8 Contention between TCNT Write and Increment 11.4.2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 11.4.3 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
