SH7014 datasheet(340/754 Pages) RENESAS

340 / 754 page

12. Serial Communication Interface (SCI)

Rev.5.00 Sep. 27, 2007 Page 306 of 716

REJ09B0398-0500

• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-

error interrupts are requested independently. The transmit-data-empty and receive-data-full

interrupts can start the direct memory access controller (DMAC) to transfer data.

12.1.2

Block Diagram

Figure 12.1 shows a block diagram of the SCI.

Parity

generation

Parity check

Transmit/

receive control

Baud rate

generator

Clock

External clock

Internal

data bus

RxD

RDR

TDR

RSR

TSR

SSR

SCR

SMR

BRR

φ/4

φ/16

φ/64

TEI

TXI

RXI

ERI

SCK

RSR

RDR

TSR

TDR

Receive shift register

Receive data register

Transmit shift register

Transmit data register

SMR

SCR

SSR

BRR

Serial mode register

Serial control register

Serial status register

Bit rate register

TxD

SCI

Module data bus

Legend:

Figure 12.1 SCI Block Diagram

SH7014 Datasheet(PDF) 340 Page - Renesas Technology Corp

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