SH7014 datasheet(343/754 Pages) RENESAS

343 / 754 page

12. Serial Communication Interface (SCI)

Rev.5.00 Sep. 27, 2007 Page 309 of 716

REJ09B0398-0500

from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1,

however, the SCI does not load the TDR contents into the TSR.

The CPU cannot read or write the TSR directly.

12.2.4

Transmit Data Register (TDR)

Bit:

Initial value:

R/W:

R/W

The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When

the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the

TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by

writing the next transmit data in the TDR during serial transmission from the TSR.

The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset

or in standby mode.

12.2.5

Serial Mode Register (SMR)

Bit:

CHR

STOP

CKS1

CKS0

Initial value:

R/W:

R/W

The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication

format and selects the clock source for the baud rate generator.

The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset

or in standby mode.

SH7014 Datasheet(PDF) 343 Page - Renesas Technology Corp