SH7014 datasheet(426/754 Pages) RENESAS

426 / 754 page

13. High Speed A/D Converter

⎯ SH7014 ⎯

Rev.5.00 Sep. 27, 2007 Page 392 of 716

REJ09B0398-0500

Table 13.7

A/D Conversion Times

CKS = 0

CKS = 1

Time

Symbol

Min

Typ

Max

Min

Typ

Max

A/D conversion start

delay time

1.5

Input sampling time

SPL

A/D conversion time

CONV

42.5

82.5

Notes: 1. Unit: states

2. Table entries are for when PWR = 1. If 200 states have not elapsed since the ADST bit

has been set, no conversions are done until after those 200 states have occurred.

When PWR = 0, add 200 states to the first A/D conversion start delay time. When two

or more conversions are performed in succession, tcp is 20 cycles when CKS = 0, and

40 cycles when CKS = 1.

The CKS bit of the ADCSR is the operation time t

CONV, but set so that this is 2 μs or greater. Table

13.8 shows the operating frequency and CKS bit settings.

Table 13.8

Operating Frequency and CKS Bit Settings

Minimum Conversion Time (

μs)

CKS

Conversion Time (States)

28 MHz

20 MHz

16 MHz

10 MHz

8 MHz

42.5

⎯

2.1

2.6

4.3

5.3

82.5

2.9

4.2

5.0

8.3

10.3

Note:

The indication "

⎯" means the setting is not available.

SH7014 Datasheet(PDF) 426 Page - Renesas Technology Corp

SH7014 Datasheet(HTML) 426 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL