SH7014 datasheet(499/754 Pages) RENESAS

499 / 754 page

16. Pin Function Controller (PFC)

Rev.5.00 Sep. 27, 2007 Page 465 of 716

REJ09B0398-0500

16.3.8

Port D Control Register L (PDCRL)

⎯ SH7016, SH7017 ⎯

Bit:

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

Initial value:

R/W:

R/W

Bit:

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Initial value:

R/W:

R/W

PDCRL is a 16-bit read/write register that selects the multiplexed pin functions for the least

significant sixteen port D pins. There are instances when these register settings will be ignored,

depending on the operation mode.

On-Chip ROM-Disabled Extended Mode:

⎯ Mode 0 (8-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.

⎯ Mode 1 (16-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.

On-Chip ROM-Enabled Extended Mode: The port D pins are shared as data I/O pins and

general I/O pins; PDCRL settings are enabled.

Single Chip Mode: The port D pins are general I/O pins; PDCRL settings are disabled.

PDCRL is initialized to H'0000 by external power-on reset but is not initialized for reset by WDT,

standby mode, or sleep mode, so the previous data is maintained.

The settings in this register are functional only in the SH7016 and SH7017. In the SH7014, there

are no pins corresponding to this register, and it should not be read or written to.

SH7014 Datasheet(PDF) 499 Page - Renesas Technology Corp

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