SH7014 datasheet(647/754 Pages) RENESAS

647 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 613 of 716

REJ09B0398-0500

BSC

Bit

Name

Value

Description

1.5 cycles

(initial value)

RAS Precharge Cycle Count

(TPC)

2.5 cycles

1 cycle

(initial value)

RAS—CAS Delay Cycle

Count (RCD)

2 cycles

2.5 cycles

(initial value)

3.5 cycles

4.5 cycles

13, 12

CAS—Before-RAS Refresh

RAS Assert Cycle Count

(TRAS1 and TRAS0)

5.5 cycles

2-cycle (no wait) external wait disabled

(initial value)

3-cycle (1 wait) external wait disabled

4-cycle (2 wait) external wait enabled

11, 10

DRAM Write Cycle Wait Count

(DWW1 and DWW0)

5-cycle (3 wait) external wait enabled

2-cycle (no wait) external wait disabled

(initial value)

3-cycle (1 wait) external wait disabled

4-cycle (2 wait) external wait enabled

9, 8

DRAM Read Cycle Wait Count

(DWR1 and DWR0)

5-cycle (3 wait) external wait enabled

No idle cycles

(initial value)

DRAM Idle Cycle Count (DIW)

1 idle cycle

Burst disabled

(initial value)

Burst Enable (BE)

DRAM high-speed page mode enabled

Access DRAM by RAS up mode

(initial value)

RAS Down Mode (RASD)

Access DRAM by RAS down mode

Byte (8-bit)

(initial value)

DRAM Bus Width

Specification (SZ0)

Word (16-bit)

9 bit

(initial value)

10 bit

11 bit

1, 0

DRAM Address Multiplex

(AMX1 and AMX0)

12 bit

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