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SH7014 Datasheet(PDF) 651 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 651 Page - Renesas Technology Corp |
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651 / 754 page ![]() Appendix A On-Chip Supporting Module Registers Rev.5.00 Sep. 27, 2007 Page 617 of 716 REJ09B0398-0500 DMAC DMA Channel Control Registers 0, 1 (CHCR0, CHCR1) H'FFFF86CC (Channel 0) H'FFFF86DC (Channel 1) 8/16/32 Bit Item 31 30 29 28 27 26 25 24 Bit name ― ― ― ― ― ― ― ― Initial value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Item 23 22 21 20 19 18 17 16 Bit name ― ― ― ― ― RL AM AL Initial value 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W Item 15 14 13 12 11 10 9 8 Bit name DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Item 7 6 5 4 3 2 1 0 Bit name ― DS TM TS1 TS0 IE TE DE Initial value 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/(W) R/W Bit Name Value Description 0 Output DRAK with active high (initial value) 18 Request Check Level (RL) 1 Output DRAK with active low 0 Outputs DACK during read cycle (initial value) 17 Acknowledge Mode (AM) 1 Outputs DACK during write cycle 0 Active high output (initial value) 16 Acknowledge Level (AL) 1 Active low output 0 Destination address fixed (initial value) 0 1 Destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 0 Destination address decremented (–1 during 8-bit transfer, –2 during 16-bit transfer, –4 during 32-bit transfer) 15, 14 Destination Address Mode 1, 0 (DM1 and DM0) 1 1 (Setting prohibited) |
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