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SH7014 Datasheet(PDF) 652 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 652 Page - Renesas Technology Corp |
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652 / 754 page ![]() Appendix A On-Chip Supporting Module Registers Rev.5.00 Sep. 27, 2007 Page 618 of 716 REJ09B0398-0500 DMAC Bit Name Value Description 0 Source address fixed (initial value) 0 1 Source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 0 Source address decremented (–1 during 8-bit transfer, –2 during 16-bit transfer, –4 during 32-bit transfer) 13, 12 Source Address Mode 1, 0 (SM1 and SM0) 1 1 (Setting prohibited) 0 External request, dual address mode (initial value) 0 1 (Prohibited) 0 External request, single address mode. External address space → external device. 0 1 1 External request, single address mode. External device → external address space. 0 Auto-request 0 1 (Prohibited) 0 MTUTGI0A 0 1 1 1 MTUTGI1A 0 MTUTGI2A 0 1 (Prohibited) 0 (Prohibited) 0 1 1 A/D ADI 0 SCI0TXI0 0 1 RXI0 0 SCI1TXI1 11 to 8 Resource Select 3 to 0 (RS3 to RS0) 1 1 1 1 RXI1 0 Low-level detection (initial value) 6 DREQ Select (DS) 1 Falling-edge detection 0 Cycle steal mode (initial value) 5 Transfer Mode (TM) 1 Burst mode 0 Specifies byte size (8 bits) (initial value) 0 1 Specifies word size (16 bits) 0 Specifies longword size (32 bits) 4, 3 Transfer Size 1, 0 (TS1, TS0) 1 1 (Prohibited) 0 Interrupt request not generated after DMATCR—specified transfer count (initial value) 2 Interrupt Enable (IE) 1 Interrupt request enabled on completion of DMATCR specified number of transfers |
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