SH7014 datasheet(654/754 Pages) RENESAS

654 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 620 of 716

REJ09B0398-0500

MTU

Timer Control Register 0 (TCR0)

H'FFFF8260

8/16/32

Bit

Item

Bit name

CCLR2

CCLR1

CCLR0

CKEG1

CKEG0

TPSC2

TPSC1

TPSC0

Initial value

R/W

Bit

Name

Value

Description

TCNT clear disabled

(initial value)

TCNT is cleared by TGRA compare-match or input

captur

TCNT is cleared by TGRB compare-match or input

capture

Synchronizing clear: TCNT is cleared in synchronization

with clear of other channel counters operating in sync.*

TCNT clear disabled

TCNT is cleared by TGRC compare-match or input

capture*

TCNT is cleared by TGRD compare-match or input

capture*

7 to 5

Counter Clear 2 to 0

(CCLR2 to CCLR0)

Synchronizing clear: TCNT is cleared in synchronization

with clear of other channel counters operating in sync*

Count on rising edges

(initial value)

Count on falling edges

4, 3

Clock Edge 1, 0

(CKEG1 and CKEG0)*

Count on both rising and falling edges

Internal clock: count with

φ/1

(initial value)

Internal clock: count with

φ/4

Internal clock: count with

φ/16

Internal clock: count with

φ/64

External clock: count with the TCLKA pin input

External clock: count with the TCLKB pin input

External clock: count with the TCLKC pin input

2 to 0

Timer Prescaler 2 to 0

(TPSC2 to TPSC0)

External clock: count with the TCLKD pin input

Notes:

1. Setting the SYNC bit of the TSYR to 1 sets the synchronization.

2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because the buffer

registers have priority and compare-match/input captures do not occur.

3. X: 0 or 1, don't care.

4. Internal clock edge selection is effective when the input clock is

φ/4 or slower. These settings are

ignored when

φ/1, or the overflow/underflow of another channel is selected for the input clock.

SH7014 Datasheet(PDF) 654 Page - Renesas Technology Corp

SH7014 Datasheet(HTML) 654 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL