SH7014 datasheet(684/754 Pages) RENESAS

684 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 650 of 716

REJ09B0398-0500

SCI

Serial Status Register (SSR)

H'FFFF81A4 (Channel 0)

H'FFFF81B4 (Channel 1)

8/16

Bit

Item

Bit name

TDRE

RDRF

ORER

FER

PER

TEND

MPB

MPBT

Initial value

R/W

R/(W)*

R/W

Note:

The only value that can be written is a 0 to clear the flag.

Bit

Name

Value

Description

TDR contains valid transmit data

Clearing conditions:

•

When 0 is written to TDRE after reading TDRE = 1

•

When DMAC writes data in TDR

Transmit Data Register Empty

(TDRE)

TDR does not contain valid transmit data

(initial value)

Setting conditions:

•

Power-on reset or standby mode

•

When the TE bit in SCR is 0

•

When data is transferred from TDR to TSR and data

can be written to TDR

RDR does not contain valid received data

(initial value)

Clearing conditions:

•

Power-on reset or standby mode

•

When 0 is written to RDRF after reading RDRF = 1

•

When DMAC reads data from RDR

Receive Data Register Full

(RDRF)

RDR contains valid received data

Setting condition: When serial reception ends normally

and receive data is transferred from RSR to RDR

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