SH7014 datasheet(681/754 Pages) RENESAS

681 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 647 of 716

REJ09B0398-0500

SCI

Serial Mode Register (SMR)

H'FFFF81A0 (Channel 0)

H'FFFF81B0 (Channel 1)

8/16

Bit

Item

Bit name

CHR

STOP

CKS1

CKS0

Initial value

R/W

Bit

Name

Value

Description

Asynchronous mode

(initial value)

Communication Mode (C/

Clocked synchronous mode

Eight-bit data

(initial value)

Character Length (CHR)

Seven-bit data*

Parity bit not added or checked

(initial value)

Parity Enable (PE)

Parity bit added and checked*

Even parity*

(initial value)

Parity Mode (O/

Odd parity*

One stop bit*

(initial value)

Stop Bit Length (STOP)

Two stop bits*

Multiprocessor function disabled

(initial value)

Multiprocessor Mode (MP)

Multiprocessor format selected

(initial value)

φ/4

φ/16

1, 0

Clock Select 1 and 0

(CKS1 and CKS0)

φ/64

Notes:

1. When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted.

2. When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity

mode (O/

E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.

3. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in

the transmitted character and parity bit combined. Receive data is checked to see if it has an even

number of 1s in the received character and parity bit combined.

4. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the

transmitted character and parity bit combined. Receive data is checked to see if it has an odd

number of 1s in the received character and parity bit combined.

5. In transmitting, a single bit of 1 is added at the end of each transmitted character.

6. In transmitting, two bits of 1 are added at the end of each transmitted character.

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