SH7014 datasheet(678/754 Pages) RENESAS

678 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 644 of 716

REJ09B0398-0500

WDT

Timer Counter (TCNT)

H'FFFF8610 (Write)*

H'FFFF8611 (Read)*

―

Bit

Item

Bit name

Initial value

R/W

Notes:

1. Write by word transfer. It cannot be written in byte or longword.

2. Read by byte transfer. It cannot be read in word or longword.

Timer Control/Status Register (TCSR)

H'FFFF8610

―

Bit

Item

Bit name

OVF

WT/

TME

―

CKS2

CKS1

CKS0

Initial value

R/W

R/(W)*

R/W

Note:

The TCSR differs from other registers in that it is more difficult to write to. See section 11.2.4,

Bit

Name

Value

Description

No overflow of TCNT in interval timer mode

(initial value)

Cleared by reading OVF, then writing 0 in OVF

Overflow Flag (OVF)

TCNT overflow in the interval timer mode

Interval timer mode: interval timer interrupt request to the

CPU when TCNT overflows

(initial value)

Timer Mode Select (WT/

IT)

Watchdog timer mode:

WDTOVF signal output externally

when TCNT overflows*

Timer disabled: TCNT is initialized to H'00 and count-up

stops

(initial value)

Timer Enable (TME)

Timer enabled: TCNT starts counting. A

WDTOVF signal

or interrupt is generated when TCNT overflows.

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