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SH7014 Datasheet(PDF) 677 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 677 Page - Renesas Technology Corp |
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677 / 754 page  Appendix A On-Chip Supporting Module Registers Rev.5.00 Sep. 27, 2007 Page 643 of 716 REJ09B0398-0500 MTU Timer Synchro Register (TSYR) H'FFFF8241 8/16/32 Bit Item 7 6 5 4 3 2 1 0 Bit name ― ― ― ― ― SYNC2 SYNC1 SYNC0 Initial value 0 0 0 0 0 0 0 0 R/W R R R R R R/W R/W R/W Bit Name Value Description 0 Timer counter (TCNTn) independent operation (TCNTn preset/clear unrelated to other channels) (initial value) 2 to 0 Timer Synchronization 2 to 0 (SYNC2 to SYNC0) 1 Timer counter synchronous operation* 1 TCNTn synchronous preset/ synchronous clear* 2 possible Notes: n = 2 to 0 1. Minimum of two channel SYNC bits must be set to 1 for synchronous operation. 2. TCNT counter clear sources (CCLR2 to CCLR0 bits of the TCR register) must be set in addition to the SYNC bit in order to have clear synchronization. |
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