SH7014 datasheet(679/754 Pages) RENESAS

679 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 645 of 716

REJ09B0398-0500

WDT

Description

Bit

Name

Value

Clock Source

Overflow Interval*

(

φ = 28.7 MHz)

φ/2

(Initial value) 17.9

μs

φ/64

573.4

μs

φ/128

1.1 ms

φ/256

2.3 ms

φ/512

4.6 ms

φ/1024

9.2 ms

φ/4096

36.7 ms

2 to 0

Clock Select 2 to 0

(CKS2 to CKS0)

φ/8192

73.4 ms

Notes:

1. Section 11.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when

TCNT overflows in the watchdog timer mode.

2. The overflow interval listed is the time from when the TCNT begins counting at H'00 until an

overflow occurs.

Reset Control/Status Register (RSTCSR)

H'FFFF8612 (Write)

H'FFFF8613 (Read)

―

Bit

Item

Bit name

WOVF

RSTE

―

Initial value

R/W

R/(W)*

R/W

Note:

Only 0 can be written in bit 7 to clear the flag.

Bit

Name

Value

Description

No TCNT overflow in watchdog timer mode

(initial value)

Cleared when software reads WOVF, then writes 0 in

WOVF

Watchdog Timer Overflow Flag

(WOVF)

Set by TCNT overflow in watchdog timer mode

Not reset when TCNT overflows

(initial value)

LSI not reset internally, but TCNT and TCSR reset

within WDT.

Reset Enable (RSTE)

Reset when TCNT overflows

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