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SH7014 Datasheet(PDF) 682 Page - Renesas Technology Corp

Part # SH7014
Description  32-Bit RISC Microcomputer
PDF  754 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Datasheet(HTML) 682 Page - Renesas Technology Corp

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Appendix A On-Chip Supporting Module Registers
Rev.5.00 Sep. 27, 2007 Page 648 of 716
REJ09B0398-0500
SCI
Serial Control Register (SCR)
H'FFFF81A2 (Channel 0)
H'FFFF81B2 (Channel 1)
8/16
Bit
Item
7
6
5
4
3
2
1
0
Bit name
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Value
Description
0
Transmit-data-empty interrupt request (TXI) is disabled *
1
(initial value)
7
Transmit Interrupt Enable
(TIE)
1
Transmit-data-empty interrupt request (TXI) is enabled
0
Receive-data-full interrupt (RXI) and receive-error interrupt
(ERI) requests are disabled*
2
(initial value)
6
Receive Interrupt Enable
(RIE)
1
Receive-data-full interrupt (RXI) and receive-error interrupt
(ERI) requests are enabled
0
Transmitter disabled*
3
(initial value)
5
Transmit Enable (TE)
1
Transmitter enabled*
4
0
Receiver disabled*
5
(initial value)
4
Receive Enable (RE)
1
Receiver enabled*
6
0
Multiprocessor interrupts are disabled
(initial value)
(normal receive operation)
MPIE is cleared when the MPIE bit is cleared to 0, or the
multiprocessor bit (MPB) is set to 1 in receive data.
3
Multiprocessor Interrupt
Enable (MPIE)
1
Multiprocessor interrupts are enabled*
7
Receive-data-full interrupt requests (RXI), receive-error
interrupt requests (ERI), and setting of the RDRF, FER, and
ORER status flags in the serial status register (SSR) are
disabled until data with the multiprocessor bit set to 1 is
received.
0
Transmit-end interrupt (TEI) requests are disabled*
8
(initial value)
2
Transmit-End Interrupt
Enable (TEIE)
1
Transmit-end interrupt (TEI) requests are enabled*
8



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