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SH7014 Datasheet(PDF) 151 Page - Renesas Technology Corp

Part # SH7014
Description  32-Bit RISC Microcomputer
PDF  754 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Datasheet(HTML) 151 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 117 of 716
REJ09B0398-0500
Bit 7
⎯DRAM Idle Cycle Count (DIW): Specifies whether to insert idle cycles, either when
accessing a different external space (CS space) or when doing a DRAM write, after DRAM reads.
Bit 7
DIW
Description
0
No idle cycles
(initial value)
1
1 idle cycle
Bit 6
⎯Reserved: This bit always read as 0. The write value should always be 0.
Bit 5
⎯Burst Enable (BE): Specifies the DRAM operation mode.
Bit 5
BE
Description
0
Burst disabled
(initial value)
1
DRAM high-speed page mode enabled
.
Bit 4
⎯RAS Down Mode (RASD): Specifies the DRAM operation mode.
Bit 4
RASD
Description
0
Access DRAM by RAS up mode
(initial value)
1
Access DRAM by RAS down mode
Bit 3
⎯Reserved: This bit read 0 after a reset. The write value should always be 0. Operation is
not guaranteed if the write value is 1.
Bit 2
⎯DRAM Bus Width Specification (SZ0): Specifies the DRAM space bus width.
Bit 2
SZ0
Description
0
Byte (8-bit)
(initial value)
1
Word (16-bit)



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