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SH7014 Datasheet(PDF) 149 Page - Renesas Technology Corp

Part # SH7014
Description  32-Bit RISC Microcomputer
PDF  754 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Datasheet(HTML) 149 Page - Renesas Technology Corp

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8. Bus State Controller (BSC)
Rev.5.00 Sep. 27, 2007 Page 115 of 716
REJ09B0398-0500
Bits 3 to 0
⎯CS Space DMA Single Address Mode Access Wait Specification (DSW3, DSW2,
DSW1, DSW0): Specifies the number of waits for CS space access (0 to 15) during DMA single
address mode accesses. These bits are independent of the W bits of the WCR1.
Bit 3
DSW3
Bit 2
DSW2
Bit 1
DSW1
Bit 0
DSW0
Description
0
0
0
0
No wait (external wait input disabled)
0
0
0
1
1 wait (external wait input enabled)
⋅⋅⋅
1
1
1
1
15 wait (external wait input enabled)
(initial value)
8.2.5
DRAM Area Control Register (DCR)
DCR is a 16-bit read/write register that selects the number of waits, operation mode, number of
address multiplex shifts and the like for DRAM control.
After a power-on reset, write the initial values to the bits in DCR and do not change the values
afterward.
Do not perform any DRAM space accesses before DCR initial settings are completed.
DCR is initialized by power-on resets to H'0000, but is not initialized by software standbys.
Bit:
15
14
13
12
11
10
9
8
TPC
RCD
TRAS1
TRAS0
DWW1
DWW0
DWR1
DWR0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
DIW
⎯
BE
RASD
⎯
SZ0
AMX1
AMX0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R
R/W
R/W
R
R/W
R/W
R/W
Bit 15
⎯RAS Precharge Cycle Count (TPC): Specifies the minimum number of cycles after
RAS is negated before next assert.
Bit 15
TPC
Description
0
1.5 cycles
(initial value)
1
2.5 cycles



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