SH7014 datasheet(150/754 Pages) RENESAS

150 / 754 page

8. Bus State Controller (BSC)

Rev.5.00 Sep. 27, 2007 Page 116 of 716

REJ09B0398-0500

Bit 14

⎯RAS-CAS Delay Cycle Count (RCD): Specifies the number of row address output

cycles.

Bit 14

RCD

Description

1 cycle

(initial value)

2 cycles

Bits 13 and 12

⎯CAS-Before-RAS Refresh RAS Assert Cycle Count (TRAS1 and TRAS0):

Specify the number of RAS assert cycles for CAS before RAS refreshes.

Bit 13

TRAS1

Bit 12

TRAS0

Description

2.5 cycles

(initial value)

3.5 cycles

4.5 cycles

5.5 cycles

Bits 11 and 10

⎯DRAM Write Cycle Wait Count (DWW1 and DWW0): Specifies the number

of DRAM write cycle column address output cycles.

Bit 11

DWW1

Bit 10

DWW0

Description

2-cycle (no wait) external wait disabled

(initial value)

3-cycle (1 wait) external wait disabled

4-cycle (2 wait) external wait enabled

5-cycle (3 wait) external wait enabled

Bits 9 and 8

⎯DRAM Read Cycle Wait Count (DWR1 and DWR0): Specifies the number of

DRAM read cycle column address output cycles.

Bit 9

DWR1

Bit 8

DWR0

Description

2-cycle (no wait) external wait disabled

(initial value)

3-cycle (1 wait) external wait disabled

4-cycle (2 wait) external wait enabled

5-cycle (3 wait) external wait enabled

SH7014 Datasheet(PDF) 150 Page - Renesas Technology Corp

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