SH7014 datasheet(184/754 Pages) RENESAS

184 / 754 page

9. Direct Memory Access Controller (DMAC)

Rev.5.00 Sep. 27, 2007 Page 150 of 716

REJ09B0398-0500

9.1.4

Table 9.2 summarizes the DMAC registers. DMAC has a total of 9 registers. Each channel has

four control registers. One other control register is shared by all channels.

Table 9.2

DMAC Registers

Channel Name

Abbrevi-

ation

R/W

Initial

Value

Address

Size

Access

Size

DMA source

address register 0

SAR0

R/W

Undefined

H'FFFF86C0 32 bit

16, 32*

DMA destination

address register 0

DAR0

R/W

Undefined

H'FFFF86C4 32 bit

16, 32*

DMA transfer count

DMATCR0 R/W

Undefined

H'FFFF86C8 32 bit

16, 32*

DMA channel

control register 0

CHCR0

R/W*

H'00000000 H'FFFF86CC 32 bit

16, 32*

DMA source

address register 1

SAR1

R/W

Undefined

H'FFFF86D0 32 bit

16, 32*

DMA destination

address register 1

DAR1

R/W

Undefined

H'FFFF86D4 32 bit

16, 32*

DMA transfer count

DMATCR1 R/W

Undefined

H'FFFF86D8 32 bit

16, 32*

DMA channel

control register 1

CHCR1

R/W*

H'00000000 H'FFFF86DC 32 bit

16, 32*

Shared

DMA operation

DMAOR

R/W*

H'0000

H'FFFF86B0 16 bit

16*

Notes: 1. Write 0 after reading 1 in bit 1 of CHCR0, CHCR1 and in bits 1 and 2 of the DMAOR to

clear flags. No other writes are allowed.

2. For 16-bit access of SAR0, SAR1, DAR0, DAR1, and CHCR0, CHCR1, the 16-bit value

on the side not accessed is held.

3. DMATCR has a 16-bit configuration: bits 0 to 15. Writing to the upper 16 bits (bits 16 to

31) is invalid, and these bits always read 0.

4. Only 16-bit access for DMAOR.

5. Do not attempt to access an empty address. If an access is attemped, the system

operation is not guarenteed.

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