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SH7014 Datasheet(PDF) 188 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 188 Page - Renesas Technology Corp |
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188 / 754 page ![]() 9. Direct Memory Access Controller (DMAC) Rev.5.00 Sep. 27, 2007 Page 154 of 716 REJ09B0398-0500 9.2.4 DMA Channel Control Registers 0, 1 (CHCR0, CHCR1) DMA channel control registers 0, 1 (CHCR0, CHCR1) is a 32-bit read/write register where the operation and transmission of each channel is designated. Bits 31 to 19 and bit 7 should always read 0. The written value should also be 0. They are initialized to 0 by a power-on reset and in software standby mode. Bit: 31 30 29 28 27 26 25 24 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 ⎯ ⎯ ⎯ ⎯ ⎯ RL AM AL Initial value: 0 0 0 0 0 0 0 0 R R R R R R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 ⎯ DS TM TS1 TS0 IE TE DE Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/(W)* R/W Note: * TE bit: Allows only 0 write after reading 1. |
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