SH7014 datasheet(191/754 Pages) RENESAS

191 / 754 page

9. Direct Memory Access Controller (DMAC)

Rev.5.00 Sep. 27, 2007 Page 157 of 716

REJ09B0398-0500

Bit 6

⎯DREQ Select (DS): Sets the sampling method for the DREQ pin in external request mode

to either low-level detection or falling-edge detection. When specifying an on-chip peripheral

module or auto-request as the transfer request source, this bit setting is ignored. The sampling

method is fixed at falling-edge detection in cases other than auto-request.

Bit 6

Description

Low-level detection

(initial value)

Falling-edge detection

Bit 5

⎯Transfer Mode (TM): Specifies the bus mode for data transfer.

Bit 5

Description

Cycle steal mode

(initial value)

Burst mode

Bits 4 and 3

⎯Transfer Size 1, 0 (TS1, TS0): Specifies size of data for transfer.

Bit 4

TS1

Bit 3

TS0

Description

Specifies byte size (8 bits)

(initial value)

Specifies word size (16 bits)

Specifies longword size (32 bits)

Prohibited

Bit 2

⎯Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the

number of data transfers specified in the DMATCR (when TE = 1).

Bit 2

Description

Interrupt request not generated after DMATCR-specified transfer count

(initial value)

Interrupt request enabled on completion of DMATCR specified number

of transfers

SH7014 Datasheet(PDF) 191 Page - Renesas Technology Corp