SH7014 datasheet(192/754 Pages) RENESAS

192 / 754 page

9. Direct Memory Access Controller (DMAC)

Rev.5.00 Sep. 27, 2007 Page 158 of 716

REJ09B0398-0500

Bit 1

⎯Transfer End Flag (TE): This bit is set to 1 after the number of data transfers specified

by the DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.

If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or clearing

of the DE bit or DME bit of the DMAOR) the TE is not set to 1. With this bit set to 1, data transfer

is disabled even if the DE bit is set to 1.

Bit 1

Description

DMATCR-specified transfer count not ended

(initial value)

Clear condition: 0 write after TE = 1 read, Power-on reset, standby

mode

DMATCR specified number of transfers completed

Bit 0

⎯DMAC Enable (DE): DE enables operation in the corresponding channel.

Bit 0

Description

Operation of the corresponding channel disabled

(initial value)

Operation of the corresponding channel enabled

Transfer mode is entered if this bit is set to 1 when auto-request is specified (RS3 to RS0 settings).

With an external request or on-chip module request, when a transfer request occurs after this bit is

set to 1, transfer is enabled. If this bit is cleared during a data transfer, transfer is suspended.

If the DE bit has been set, but TE = 1, then if the DME bit of the DMAOR is 0, and the NMI or

AE bit of the DMAOR is 1, transfer enable mode is not entered.

SH7014 Datasheet(PDF) 192 Page - Renesas Technology Corp