SH7014 datasheet(194/754 Pages) RENESAS

194 / 754 page

9. Direct Memory Access Controller (DMAC)

Rev.5.00 Sep. 27, 2007 Page 160 of 716

REJ09B0398-0500

Bit 1

⎯NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the

DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels

are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by a 0 write after

1 read.

Bit 1

NMIF

Description

No NMI interrupt, DMA transfer enabled

(initial value)

Clearing condition: Write NMIF = 0 after reading NMIF = 1

NMI has occurred, DMC transfer prohibited

Set condition: NMI interrupt occurrence

Bit 0

⎯DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When

the DME bit and DE bit of the CHCR for the corresponding channel are set to 1, that channel is

transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are

suspended.

Even when the DME bit is set, when the TE bit of the CHCR is 1, or its DE bit is 0, transfer is

disabled in the case of an NMI of the DMAOR or when AE = 1.

Bit 0

DME

Description

Disable operation on all channels

(initial value)

Enable operation on all channels

SH7014 Datasheet(PDF) 194 Page - Renesas Technology Corp