SH7014 datasheet(196/754 Pages) RENESAS

196 / 754 page

9. Direct Memory Access Controller (DMAC)

Rev.5.00 Sep. 27, 2007 Page 162 of 716

REJ09B0398-0500

Figure 9.2 is a flowchart of this procedure.

Normal end

Does

NMIF = 1, AE = 1,

DE = 0, or DME

= 0?

Bus mode,

transfer request mode,

DREQ detection selection

system

Initial settings

(SAR, DAR, DMATCR,

CHCR, DMAOR)

Transfer (1 transfer unit);

DMATCR

− 1 → DMATCR, SAR and DAR

updated

DEI interrupt request (when IE = 1)

Yes

Start

Transfer aborted

Notes: 1.

In auto-request mode, transfer begins when NMIF, AE, and TE are all 0,

and the DE and DME bits are set to 1.

DREQ level detection in burst mode (external request) or cycle-steal

mode.

DREQ edge detection in burst mode (external request), or auto-request

mode in burst mode.

DMATCR = 0?

Transfer request

occurs?*1

DE, DME = 1 and

NMIF, AE, TE = 0?

Does

NMIF = 1, AE = 1,

DE = 0, or DME

= 0?

Transfer ends

Figure 9.2 DMAC Transfer Flowchart

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