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SH7014 Datasheet(PDF) 199 Page - Renesas Technology Corp

Part # SH7014
Description  32-Bit RISC Microcomputer
PDF  754 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7014 Datasheet(HTML) 199 Page - Renesas Technology Corp

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9. Direct Memory Access Controller (DMAC)
Rev.5.00 Sep. 27, 2007 Page 165 of 716
REJ09B0398-0500
When an on-chip peripheral module's interrupt request signal is used as a DMA transfer request
signal, interrupts for the CPU are not generated.
When a DMA transfer is conducted corresponding with one of the transfer request signals in table
9.4, it is automatically discontinued. In cycle steal mode this occurs in the first transfer, and in
burst mode with the last transfer.
9.3.3
Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. The channel priority order is fixed at channel
0 > channel 1.
9.3.4
DMA Transfer Types
The DMAC supports the transfers shown in table 9.5. It can operate in the single address mode, in
which either the transfer source or destination is accessed using an acknowledge signal, or dual
address mode, in which both the transfer source and destination addresses are output. The DMAC
has two bus modes: cycle-steal mode and burst mode.
Table 9.5
Supported DMA Transfers
Destination
Source
External Device
with DACK
External
Memory
Memory-
Mapped
External
Device
On-Chip
Memory
On-Chip
Peripheral
Module
External device with DACK Not available
Single
Single
Not available
Not available
External memory
Single
Dual
Dual
Dual
Dual
Memory-mapped external
device
Single
Dual
Dual
Dual
Dual
On-chip memory
Not available
Dual
Dual
Dual
Dual
On-chip peripheral module
Not available
Dual
Dual
Dual
Dual
Notes: 1. Single: Single address mode
2. Dual: Dual address mode



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