SH7014 datasheet(198/754 Pages) RENESAS

198 / 754 page

9. Direct Memory Access Controller (DMAC)

Rev.5.00 Sep. 27, 2007 Page 164 of 716

REJ09B0398-0500

On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer

request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 9.4,

there are eight transfer request signals: three from the multifunction timer pulse unit (MTU),

which are compare match or input capture interrupts; the receive data full interrupts (RxI) and

transmit data empty interrupts (TxI) of the two serial communication interfaces (SCI); and the A/D

conversion end interrupt (ADI) of the A/D converter. When DMA transfers are enabled (DE = 1,

DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request

signal.

The transfer request source need not be the data transfer source or transfer destination. However,

when the transfer request is set by RxI (transfer request because SCI's receive data is full), the

transfer source must be the SCI's receive data register (RDR). When the transfer request is set by

TxI (transfer request because SCI's transmit data is empty), the transfer destination must be the

SCI's transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the data

transfer destination must be the A/D converter register.

Table 9.4

Selecting On-Chip Peripheral Module Request Modes with the RS Bits

RS3 RS2 RS1 RS0

DMAC Transfer

Request Source

DMA Transfer

Request SignalSource

Destin-

ation

Bus Mode

MTU*

TGI0A

Any*

Burst/cycle steal

MTU*

TGI1A

Any*

Burst/cycle steal

MTU*

TGI2A

Any*

Burst/cycle steal

Prohibited

A/D

ADI

ADDR*

Any*

Burst/cycle steal

SCI0*

3 transmit block

TxI0

Any*

TDR0

Burst/cycle steal

SCI0*

3 receive block

RxI0

RDR0

Any*

Burst/cycle steal

SCI1*

3 transmit block

TxI1

Any*

TDR1

Burst/cycle steal

SCI1*

3 receive block

RxI1

RDR1

Any*

Burst/cycle steal

Notes: 1. External memory, memory-mapped external device, on-chip memory, on-chip

peripheral module (excluding DMAC, BSC).

2. MTU: Multifunction timer pulse unit.

3. SCI0, SCI1: Serial communications interface.

4. ADDR: A/D converter's A/D register.

In order to output a transfer request from an on-chip peripheral module, set the relevant interrupt

enable bit for each module, and output an interrupt signal.

SH7014 Datasheet(PDF) 198 Page - Renesas Technology Corp

SH7014 Datasheet(HTML) 198 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL