SH7014 datasheet(234/754 Pages) RENESAS

234 / 754 page

10. Multifunction Timer Pulse Unit (MTU)

Rev.5.00 Sep. 27, 2007 Page 200 of 716

REJ09B0398-0500

Bits 7 to 5

⎯Counter Clear 2 to 0 (CCLR2 to CCLR0): Select the counter clear source for the

TCNT counter.

Channels 0

Bit 7

CCLR2

Bit 6

CCLR1

Bit 5

CCLR0

Description

TCNT clear disabled

(initial value)

TCNT is cleared by TGRA compare-match or input capture

TCNT is cleared by TGRB compare-match or input capture

Synchronizing clear: TCNT is cleared in synchronization with clear of

other channel counters operating in sync.*

TCNT clear disabled

TCNT is cleared by TGRC compare-match or input capture*

TCNT is cleared by TGRD compare-match or input capture*

Synchronizing clear: TCNT is cleared in synchronization with clear of

other channel counters operating in sync*

Notes: 1. Setting the SYNC bit of the TSYR to 1 sets the synchronization.

2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because

the buffer registers have priority and compare-match/input captures do not occur.

Channels 1, 2

Bit 7

Reserved*

Bit 6

CCLR1

Bit 5

CCLR0

Description

TCNT clear disabled

(initial value)

TCNT is cleared by TGRA compare-match or input capture

TCNT is cleared by TGRB compare-match or input capture

Synchronizing clear: TCNT is cleared in synchronization with

clear of other channel counters operating in sync*

Notes: 1. The bit 7 of channels 1 and 2 is reserved. It always reads 0, and cannot be modified.

2. Setting the SYNC bit of the TSYR to 1 sets the synchronization.

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