SH7014 datasheet(237/754 Pages) RENESAS

237 / 754 page

10. Multifunction Timer Pulse Unit (MTU)

Rev.5.00 Sep. 27, 2007 Page 203 of 716

REJ09B0398-0500

Channel 2

Bit 2

TPSC2

Bit 1

TPSC1

Bit 0

TPSC0

Description

Internal clock: count with

φ/1

(initial value)

Internal clock: count with

φ/4

Internal clock: count with

φ/16

Internal clock: count with

φ/64

External clock: count with the TCLKA pin input

External clock: count with the TCLKB pin input

External clock: count with the TCLKC pin input

Internal clock: count with

φ/1024

Note:

These settings are ineffective when channel 2 is in phase counting mode.

10.2.2

Timer Mode Register (TMDR)

The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU

has three TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset

or the standby mode.

Channel 0: TMDR0

Bit:

⎯

BFB

BFA

MD3

MD2

MD1

MD0

Initial value:

R/W:

R/W

Channels 1, 2: TMDR1, TMDR2

Bit:

⎯

MD3

MD2

MD1

MD0

Initial value:

R/W:

R/W

SH7014 Datasheet(PDF) 237 Page - Renesas Technology Corp

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