SH7014 datasheet(248/754 Pages) RENESAS

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10. Multifunction Timer Pulse Unit (MTU)

Rev.5.00 Sep. 27, 2007 Page 214 of 716

REJ09B0398-0500

Bits 3 to 0

⎯I/O Control A3 to A0 (IOA3 to IOA0): These bits set the TGR2A register function.

Bit 3

IOA3

Bit 2

IOA2

Bit 1

IOA1

Bit 0

IOA0

Description

Output disabled

(initial value)

Initial output is 0 Output 0 on compare-match

Output 1 on compare-match

TGR2A

is an output

compare

Toggle output on compare-match

Output disabled

Initial output is 1 Output 0 on compare-match

Output 1 on compare-match

Toggle output on compare-match

Input capture on rising edge

Input capture on falling edge

Capture input

source is the

TIOC2A pin

Input capture on both edges

TGR2A

is an input

capture

Input capture on rising edge

Input capture on falling edge

Input capture on both edges

10.2.4

Timer Interrupt Enable Register (TIER)

The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel.

The MTU has three TIER registers, one each for channel. TIER is initialized to H'40 by a reset or

by standby mode.

Channel 0: TIER0

Bit:

TTGE

⎯

TCIEV

TGIED

TGIEC

TGIEB

TGIEA

Initial value:

R/W:

R/W

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